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Changing the world, one nanometer at a time

A lithography machine for manufacturing chips. Lithography has become the most complex stage in the chip manufacturing requiring sub-nonometer precision, that is to say atomic size precision. Image credit: ASML

I found the header for this post on the website of ASML, a company at the leading edge of lithography technology, the engine of the semiconductor industry. They have a wide range of lithographic systems including the most advanced Extreme UltraViolet Lithographic systems (EUVL) using wavelength of 13.5 nm. With this systems (they are really, really, expensive, a single machine costing in the range of 150 million $!) it is possible to obtain a 3nm “size”, that is in the order of 30 atoms side by side.

Interestingly, this high resolution requires both hardware and software, without software it wouldn’t be possible to get down to this size. Actually, thanks to software ASML expects to deliver even better systems thus sustaining the evolution towards denser and denser chips (this translates into les power consumption and faster -parallel- processing).

I spent some time surfing the ASML website (interesting one!) after reading a Wired article with the intriguing -and misleading- title: “The 150 million $ machine keeping Moore’s law alive”. It is obviously intriguing – how couldn’t it be an article on the extension of the Moore’s law?- but unfortunately it is misleading.

Moore’s law called for a squeezing transistors and a parallel decrease of cost per transistor at a rate of halving every 18 months. This prediction held for over 50 years but broke down in economic terms some five years ago and in “squeezing” terms 4 years ago. The squeezing goes on at a much smaller pace and the cost per transistor is rising at these technology edge.

Nevertheless, the article makes for an interesting reading.

Most notable, as I mentioned, is the fact that where lithographic machines are facing physical barriers software may step it to overcome, at least to a point, those barriers. For sure the semiconductor industry has already circumvented physical constraints in the 2 dimensional wafer by moving up to the third dimension (watch the clip) and researchers are busy looking into 2 dimensional materials, like graphene and molybdenum disulfide, to pack more transistors in a given space. Results, in terms of possibility, have been achieved but they are still far from industrial exploitation.

About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the New Initiative Committee and co-chairs the Digital Reality Initiative. He is a member of the IEEE in 2050 Ad Hoc Committee. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.