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Chips for AI training

An “exploded” representation of the D1 Dojo chip designed by Tesla, produced by TSMC, to speed up the training of AI. Image credit: Tesla

For quite some time the “chip” business was restricted to very few companies that were able to invest huge capitals in the design and manufacturing and because of that huge investment required a big market to sell their products. That led to the design and production of “one-size-fits-all”, in other words of chips that could be used in any application. The downside of this trend was that on the one hand the chips available were usually under-utilised (a given application area was unlikely to need all the stuff packed in the chip) and on the other hand they were not customised (made efficient) to a specific task.

The world is changing, also thanks to a revolution in chip design (the big foundries are still there). Companies can design ASIC -Application Specific Integrated Circuits- that can be much more efficient for the task they have to serve.

The announcement of Tesla, a car manufacturing company, of the development of D1, is a point in case. The chip embeds 50 billion transistors and has been designed mimicking some functionalities of the Dojo supercomputer that Tesla is using to train AI software (Tesla cars are computers on wheels with a brain made of AI). Tesla needed a more effective way to train its AI software and the D1 has been designed to focus specifically on AI training, with 362 TFLOPS (at 16 Floating point instruction) of processing power (watch the clip).

The chip is not the usual “chip” you may imagine in terms of size, it looks more like a full board (as shown in the clip). It is made up of functional unites replicated and connected in such a way to maximise the efficiency from the point of view of AI training (where the software needs to explore several paths, confront them and pick up the ones that looks best, again and again till it converge on a solution pattern).



About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the New Initiative Committee and co-chairs the Digital Reality Initiative. He is a member of the IEEE in 2050 Ad Hoc Committee. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.