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Designing chips for AI

3rd gen Xeons chip, designed with AI support in mind. Notice the back of the chip with all the connectors. Image credit: Intel

Data Centres are growing in size and processing capacity to manage the increased size and flow of data. As the Clouds they are hosting are evolving to perform more processing intensive tasks and in particular the ones involved in artificial intelligence -training, inferencing- there is an interest for chips that can better support these activities.

Here lays the interest for the Intel announcement of the 3rd generation of Xeon chips specifically designed to support AI intensive processing.

These chips are using 14nm technology, hence they are not at the leading edge with respect to etching dimension but support bfloat 16 instruction set (this is a compact numeric format that can achieve processing effectiveness similar at FP32 at a lower price point, something that is very important in large data centres). The chips are offered with 16 or 28 cores supporting multi-thread (32 to 56 respectively) and embed 38.5MB of cache memory (don’t be fooled into thinking that 38MB is peanuts, that is a cache memory used to support processing inside the chip, not a data storage) and their clock speed of 2.3 GHz can be boosted as needed up to 4.3 GHz. This is a very nice feature since one of the big cost of data centre is powering the chips (electricity) and cooling them (air conditioning). By keeping the clock speed at 2.3 GHz and boosting it only when there is a need the power consumption and dissipation is greatly reduced making them ideal for use in data centres.

Also inportant is the software backward compatibility (not 100% but according to Intel only minor changes will be required).

This news is interesting because it shows the trend towards commoditising artificial intelligence that becomes an integral feature of data centres.

About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the New Initiative Committee and co-chairs the Digital Reality Initiative. He is a member of the IEEE in 2050 Ad Hoc Committee. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.