I don’t know about you, but when I saw this image on IEEE Spectrum (read the article, it is really worth your time) it reminded me of teeth radiography… It is not. It is actually an image of a novel type of transistors whose gate size is 3nm, the smallest size we have been able to use so far for manufacturing transistors.
Current leading edge transistor manufacturing has reached 7nm and work is on to deliver 5nm in 2020. We are very very close to the limit where drain current can overcome the insulating region of the transistor (meaning it
won’t work anymore). Over the last decade researchers have worked out alternative shapes of the ensemble (see figure). A transistor is a very simple device in terms of understanding at conceptual level how it works. I usually compare it to faucet: there are basically three parts: an entry point for the water, an exit point and the handle. The handle controls the flow of water, from 0 to full (1).
A transistor is the same. You have a wire bringing in the electrons, a wire taking them out and a third one acting as the handle. This “handle” operates by applying a voltage. If big enough the gate opens and electrons flow. The tricky issue is to make sure that electrons are flowing only when the handle say so. As the junction gets smaller and smaller electrons tend to jump from the incoming to the outgoing wire, independently of the “handle”.
What researchers have done is to create a gate and a handle that can control much better the electrons flow by creating a nanosheet structure. This has allowed the shrinking of the gate to 3nm, an amazing feat indeed (just 5 years ago the general feeling was that going below 7 nm would have been impossible using silicon and alternative materials (like graphene) should be found.
Notice that this is not extending the Moore’s Law: we manage to decrease the size but at the same time we are no longer able to decrease the cost per transistor. That stopped in 2014/2015 so I take that date as the end of the line of Moore’s Law.