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Nanosheet Transistor: the last blip of the fading Moore’s Law

Nanosheet field-effect transistors flow current through multiple stacks of silicon that are completely surrounded by the transistor gate. The design reduces avenues for current to leak through and boosts the amount of current the device can drive. Credit: IEEE Spectrum and IBM

I don’t know about you, but when I saw this image on IEEE Spectrum (read the article, it is really worth your time) it reminded me of teeth radiography… It is not.  It is actually an image of a novel type of transistors whose gate size is 3nm, the smallest size we have been able to use so far for manufacturing transistors.

Current leading edge transistor manufacturing has reached 7nm and work is on to deliver 5nm in 2020. We are very very close to the limit where drain current can overcome the insulating region of the transistor (meaning it

Evolution of the transistor architecture. Image credity: Emily Cooper

won’t work anymore). Over the last decade researchers have worked out alternative shapes of the ensemble (see figure). A transistor is a very simple device in terms of understanding at conceptual level how it works. I usually compare it to faucet: there are basically three parts: an entry point for the water, an exit point and the handle. The handle controls the flow of water, from 0 to full (1).

A transistor is the same. You have a wire bringing in the electrons, a wire taking them out and a third one acting as the handle. This “handle” operates by applying a voltage. If big enough the gate opens and electrons flow. The tricky issue is to make sure that electrons are flowing only when the handle say so. As the junction gets smaller and smaller electrons tend to jump from the incoming to the outgoing wire, independently of the “handle”.

What researchers have done is to create a gate and a handle that can control much better the electrons flow by creating a nanosheet structure. This has allowed the shrinking of the gate to 3nm, an amazing feat indeed (just 5 years ago the general feeling was that going below 7 nm would have been impossible using silicon and alternative materials (like graphene) should be found.

Notice that this is not extending the Moore’s Law: we manage to decrease the size but at the same time we are no longer able to decrease the cost per transistor. That stopped in 2014/2015 so I take that date as the end of the line of Moore’s Law.

About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the Industry Advisory Board within the Future Directions Committee and co-chairs the Digital Reality Initiative. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.