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New SSD with 100+ layers enters production

256GB 3-bit V-NAND with over 100 layers. Image credit: Samsung

It was September 12th, 1958, when the first integrated chip was demonstrated by Jack Kilby at Texas Instrument (for the record, that first chip was using germanium, not silicon. Robert Noyce few months after that first chip was able to create one based on silicon). It took 12 more years to have the first microchip, the Intel 4040.

After more than fifty years of unrelenting progress we reached a limit in how much we can squeeze transistors on a sliver of silicon AND decrease the cost per transistors (around 2015), so scientists have been looking for different approaches to increase the number (read performance) of chips and one of the way is to move into the third dimension.

Industry started to created multi-layer chips so that what you cannot make in terms of density increase in a surface can be made in volume (this has been applied to memory chip to increase storage performance).
Now Samsung has announced the production of the first 256GB 3-bit V-NAND. This is the sixth generation of V-NAND and it follows the previous one in just 13 months, showing an acceleration in evolution (the previous generation were spaced by 17 months). It has been designed with 136 layers, a 40% increase from version 5.

This increases read and write speed (45µs and 450µs respectively) and at the same time decreases power consumption by more than 15%.

The 512GB chip will follow suit.

These improvements are both a godsend for the management of the flood of data in big data centres as well as an enabler of the shift towards clouds at the edge, fog. The increased availability of storage in our mass market devices is slowly, but inevitably, changing the data network architectures and a pervasive 5G transferring the control from the network to the edges will take full advantage of this although I expect a full blown revolution in architectures to become prevalent beyond 2030 when 6G will be the talk of the town.

The Moore’s law is dead, long live to Moore’s law!

About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the New Initiative Committee and co-chairs the Digital Reality Initiative. He is a member of the IEEE in 2050 Ad Hoc Committee. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.