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Tiniest transistor – yet: 2.5 nm

Using a new manufacturing technique, MIT researchers fabricated a 3-D transistor less than half the width of today’s slimmest commercial models, which could help cram far more transistors onto a single computer chip. Pictured is a cross-section of one of the researchers’ transistors that measures only 3 nanometers wide. Image credit: MIT

In spite of the fact that the Moore’s law has reached its ending point, researchers are still working on finding alternatives that would push its limits.

The present most advanced chips in terms of density are already doing that. Basically the Moore’s law stopped in 2015 in terms of cost vs density (you cannot keep increasing density and decrease cost at the same time) and it stopped in 2017 in terms of density (you cannot keep decreasing the size of the transistor to increase density). On this latter limit that was placing a limit around 14nm researchers have already found a way of cheating: today we have 7nm transistors chips (as an example in the latest iPhones) but they are actually transistors that are rotated 90°! If you want to place more transistor on a chip, hence increase density, exploit the third dimension! You can manufacture a transistor that is 220 nm (wow! that’s huge!) but just 7nm thick. Then you rotate it so that the 7nm is the space taken horizontally and the 220nm go vertically. In this way you can increase the surface density! Smart, isn’t it?

The resulting shape of the surface, when observed with an electron microscope looks like a sea of fins, each one a transistor, and that’s why this transistors are called FinFET 3D transistors.

Now researchers at MIT have managed to create FinFET 3D transistors that are thinner, down to 2.5nm (but still tall because you need enough surface to control the flow of electrons without having to face quantum uncertainty).

They did that by perfecting thermal ALE, Atomic Layer Etching, a technology invented at the University of Colorado in 2016. Rather than using chemicals to remove unwanted material (etching) from the silicon substrate, ALE uses plasma with high energy ion to strip away from a surface unwanted atoms. This sometimes lead to removing atoms that should not be removed, hence you have to use more materials to keep statistically on the safe side. With thermal ALE the removal of atoms is much more precise so you can use less atoms to create a transistor.

At MIT they perfected this technology applying it to IndiumGalliumArsenide rather than silicon, a compound already used in some chips and managed to get down to a “fin” thickness below 5nm on average, actually as tiny as 2.5nm. This allows for increased chip density (and all the nice related properties of using lower power and increasing performances).

What is really important is that this technology can be used in current manufacturing processes, which is not the case of graphene based transistors that would be potentially much smaller (sub nm size!) but that can’t be manufactured through industrial processes right now.

About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the Industry Advisory Board within the Future Directions Committee and co-chairs the Digital Reality Initiative. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.