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Portable neural network devices

Image-recognition simulation. (Left) A 3-layer multilayer-perception neural network with black and white input signal for each layer in algorithm level. The inner product (summation) of input neuron signal vector and first synapse array vector is transferred after activation and binarization as input vectors of second synapse arrays. (Right) Circuit block diagram of hardware implementation showing a synapse layer composed of epiRAM crossbar arrays and the peripheral circuit. Credit: Shinhyun Choi et al./Nature Materials

I remember, it was a long time ago, the discussion on the advantage of going digital in sound coding (and then reproduction) and we actually ended up with digital winning hands down in all the music sector. Still a number of people resisted the idea claiming that analogue remained better for the continuous nuances it could provide, versus the chopping characteristics you get when converting a wave into a series of zeros and ones. The digital supporters said, with a certain reason, that if the chopping caused by digitalisation was below our human detection capability (you can’t tell the difference) well it was a moot discussion. Still the analogue folks maintained their position.

This came to my mind as I saw a paper presenting the results of researchers at MIT on creating an analogue chip to perform image recognition (specifically tested on handwriting recognition). Our brain is basically an analogue structure, although over and over we are trying to relate neurones and synapses to transistors and bits. The idea is that a synapse triggers a signal or it does not trigger it, a neurone fires or does not fire. These map nicely onto 0 and 1. The situation, however, is quite more fuzzy and this mapping into 0s and 1s is not perfect.

In our brain there is a computation based on the strength of impulses that does not match with the conversion into 0s and 1s. There is quite a bit in between.

We have seen a number of neuromorphic chips, like IBM  SyNAPSE,  that aims at mimicking the brain neuronal structure/operation and they perform quite well. We have seen progress in memristors, where memory and computation merges like it happens, in a way, in a neurone. All of these have led to better way of computation particularly in areas like artificial intelligence -deep learning- applied to problems like image recognition. But we are not there, yet.

In these neuromorphic chips the exchange among the various parts does not occur in terms of 0s and 1s, rather through gradient of current. The problem is the difficulty in controlling these various gradients. The MIT researchers have been able to create a chip made with silicon germanium that is able to control accurately the flow of current. Instead of using an amorphous material as synapse in the chip the researchers have designed an epitaxial random access memory creating a structure partly based on germanium and partly on silicon. These two materials create structures with slightly different dimensions and this difference is used to obtain a funnel through which ions (current) can flow in a very controllable way.

They have tested the chip in the handwriting recognition obtaining an accuracy of 95%, an amazingly good result.

Interestingly, this chip can make portable neural network devices possible, which means that in certain domains, like image recognition (a most important area for autonomous systems, like self driving cars), computations that today require a supercomputer would become possible in the palm of our hand.

About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the New Initiative Committee and co-chairs the Digital Reality Initiative. He is a member of the IEEE in 2050 Ad Hoc Committee. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.