Home / Blog / The Atomristor is here!

The Atomristor is here!

Schematic of atomristor memory sandwich based on molybdenum sulfide in a form of a single-layer atomic sheet grown on gold foil. Blue: Mo; yellow: S. Credit: Ruijing Ge et al./Nano Letters

The Moore’s law has reached its endpoint (since 2014 the economics no longer works, i.e. the cost per transistor no longer halves as its dimension shrinks and its shrinking is also slowing down). Researchers are at work to find alternative to silicon and to current architectures.
One way being explored is to use monolayer – single atom- structures like graphene and molybdenum sulfide where the electrons are moving on the surface of the layer and encounter minimal resistance (plasmonics). This leads to much less heat dissipation, lower energy requirement and faster operation. And, of course, it shrinks the overall dimension (current transistors are 3D entities made up of -roughly- a thousand atoms. Notice that we have seen claim of a single molecule acting as a transistor, hence with very few atoms, however in practice these very few atoms need a substrata to hold them. In currently manufactured chips we have at least 1,000 atoms per transistor, not taking into account the casing. In a cubic mm there are some 121 billion billions atoms -of silicon- and the Intel high density chips contain 100 million transistors in a square mm and their thickness is in the order of 10nm, hence by making a rough division you will end up with a few million atoms per transistor but that is due to the “filling” and it would apply to any architecture that can be manufactured, so the 1,000 atoms per transistor is a reasonable figure one can use to compare with alternative).

In the last decade researchers have developed the memristore, a transistor that is capable of memorising its previous activities and that computes new input based on those previous activities, like our neurones do. This adds functionality to the transistor and it becomes useful in certain types of processing. In this case one can say that it is not just a matter of reducing the size of the transistor but also of increasing its functionality so that you need less transistors to perform a certain function.

This is what has to be taken into account when reading the paper written by a team of electrical engineers at the University of Austin Texas reporting on their result of creating what they have named an Atomristor.

They managed to create a monolayer structure (one molecule thick) made of molybdenum sulfide to create a memristore. Basically they demonstrated that it is possible to create a flat memristore, just 1.5 nm thick.

They see the increased density of memory and processing that can be created using this technology as a fundamental step towards the implementation of chips that can have a functional processing capability au pair with the one of our brain.

Notice that the qualification “functional” is crucial: chips today are much faster than our neurones but functionally speaking they lag behind (image recognition by a computer today is better than our image recognition but requires way more energy than what our brain uses).

Notice, also, that our brain processing is hugely parallel and each step is influencing each other steps so a one to one comparison is not possible.

Are we going to develop machines that have better computation capabilities that our brain has? Sure in terms of speed and quantity and this has been true for the last 10 years, but the functional processing capability of our brain is still better although in fewer and fewer areas and it is likely to be superseded by machines in the coming decades.

The goal now is to learn harvesting this machines growing intelligence to grow our intelligence, rather than displacing our…

About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the New Initiative Committee and co-chairs the Digital Reality Initiative. He is a member of the IEEE in 2050 Ad Hoc Committee. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.