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5nm transistors

A scan of IBM Research Alliance’s 5nm transistor, built using an industry-first process to stack silicon nanosheets as the device structure. Credit: IBM

Back in 1964 Moore’s saw the increasing number of transistors that could be squeezed onto a chip. At that time the number was around 100 transistors, a tremendous increase from the 4 transistors that Fairchild managed to put on a chip in 1960!
Today we have chips with several billions of transistors (7.2 billions in the Intel Broadwell-EP Xeon chip) and IBM has announced a new manufacturing process that will be able to squeeze 30 billion transistors on a single chip.

This feat is the result of a cooperation of IBM with Globalfoundries and Samsung and it is based on nanosheets of silicon staked to support 5nm transistors.

This is a novel approach to manufacture transistors, departing from the present FinFET architecture that can be pushed down to 7nm transistors (and 20 billion of them on a chip). According to IBM announcement, the 40% increase in density will create a parallel increase in computation performance at the same amount of energy usage, or turning it around it may extend the life of your smartphone battery to 2-3 days (assuming you will keep using your cell phone as you are using it today, which of course will not be the case…).

The manufacturing is based on the same Extreme Ultraviolet Lithography used in 7nm FinFET transistors manufacturing (current leading edge commercial transistor size is 10nm, but 7nm FinFET were demonstrated by IBM in 2015) but the FinFET architecture would not sustain current flow between transistors at this size.

In the announcement IBM is explicitly pointing to cognitive computing as application area (watch the clip), which means, actually, several areas of application including self driving cars, and more generally autonomous systems, , medical image analyses, 5G cognitive radio, smart IoT and much more.

About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the Industry Advisory Board within the Future Directions Committee and co-chairs the Digital Reality Initiative. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.