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1 TB on a postage stamp

There was a time when I traveled from Turin to Venice (400 km away) bringing along a card storing 8kB. That card was about 2kg, its size was 30x40cm and the technology used was magnetic-core memory. That was in 1971.
I remembered that as I read a news from Rice University on their new silicon oxide memory that can become the next generation of storage support, able to store 1TB in a size of a postage stamp. In 43 years the capacity has increased by a factor of 125 million times, to carry one TB of storage using those 1971 memory card I would have needed load on the train 250,000 tons of storage, pretty inconvenient! And if you are curious about the cost… well it would have cost 600 Billion $!
This amazing progress has been made possibile by refinement of production technology, refinement of technology used and change in technology.
At Rice, researchers have worked for a few year now on Resistive Random Access Memory, RRAM, first created in 2010. The RRAM is based on the principle that a specific dielectric inserted between two conductor when subject to a sufficiently high voltage creates tiny conduction pathways. The presence, or absence, of these pathways may be used to characterise that "cell" has storing a 1 or a 0.
The problem of the original RRAM was the high voltage required to create the conduction pathways, over 20V. That is way to high with respect to today’s circuits.
What Rice researchers are now announcing is a new type of dielectric material based on porous silicon oxide that slash the requirement for high voltage: 2V are sufficient to create the conduction pathways and this, along with other refinements brings RRAM in the domain of mass market production.
A comparison among this technology and others has clearly shown advantages for this in terms of energy requirement, speed and density.  Also packaging is better with RRAM. In normal flash memory you need three wires per storage cell. This makes stacking of cells more complex. Samsung is working on stacking and it is expecting to reach eventually 24 layers (thus multiplying by 24 current storage capacity). With RRAM you only need two wires per storage cell and that greatly simplify stacking. According to researchers at Rice one could stack hundreds of layers in a single chip, thus further increasing storage capacity per chip.
It is expected to see RRAM replacing Flash Memory by the end of this decade.

About Roberto Saracco

Roberto Saracco fell in love with technology and its implications long time ago. His background is in math and computer science. Until April 2017 he led the EIT Digital Italian Node and then was head of the Industrial Doctoral School of EIT Digital up to September 2018. Previously, up to December 2011 he was the Director of the Telecom Italia Future Centre in Venice, looking at the interplay of technology evolution, economics and society. At the turn of the century he led a World Bank-Infodev project to stimulate entrepreneurship in Latin America. He is a senior member of IEEE where he leads the New Initiative Committee and co-chairs the Digital Reality Initiative. He is a member of the IEEE in 2050 Ad Hoc Committee. He teaches a Master course on Technology Forecasting and Market impact at the University of Trento. He has published over 100 papers in journals and magazines and 14 books.